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Rapport Ircam 4/78, 1978
Copyright © Ircam - Centre Georges-Pompidou 1978
The oscillator phase is calculated by a 24 bit accumulator which provides a frequency resolution of about .002 Hz. The phase is used as the address to a 16k word x 14 bit wave shape table. The samples in wave shape table are loaded by the LSI- 11 so that any wave shape may be used. This size table produces about 84 db signal to noise ratio. Additionally, the 16k word table may be divided into two independent 8k tables, four 4k tables, or one 8k and two 4k tables. A control word for each oscillator is used to specify the size of the table and which table is used by that oscillator. Thus, up to four different wave shapes are available simultaneously. One of the wave table sections may be loaded while other sections are being used.
The 14 bit wave table output is multiplied by a 16 bit (signed) amplitude function, and 24 bits of the resulting product are retained. An array of 15 general purpose registers is provided to interconnect oscillators and combine their signals. A 16th register is available as a source of "zeros" and as a sink for unused output data. Each oscillator accesses the array four times. The actual registers used are specified by different four bit fields in the oscillator control word. The oscillator output may be added to the contents of any register and the sum loaded into any other register.
The oscillator frequency and amplitude values are generated by ramp processes that calculate new values at a 4kHz rate. Each ramp is controlled by 4 words in LSI- 11 address space: the start (current) value, the final value, the increment value, and a control word. The increment is added (4000 times per second) to the start until the final is equaled or exceeded, then the final value is continually used until new values are loaded by the LSI- 11. Since 24 bit registers are used, ramp times as long as 1/2 hour are available. Any combination of positive and negative values may be specified. There is full protection against all types of overflow.
Any ramp process may be optionally enabled to generate an LSI- 11 interrupt when the final value is reached. A First In First Out (FIFO) buffer structure is included to queue the interrupt events so that only one address need be accessed to find which ramps have reached their final value.
The current ramp value may be optionally exponentiated before it is used as the amplitude (or frequency). A read only memory conversion table and shift technique yields .2% accuracy over a 90db (or 15 octave) dynamic range. Thus, exponential attacks and decays are simply produced and octave frequency scaling is easily done.
Each oscillator's phase is calculated using two inputs: the ramp process and the data from one of the 16 registers. Thus, the output of one oscillator may be used to linearly modulate the frequency of another oscillator.
As shown in Fig. 1, the multiplier may be used in some optional ways. Data in an array register (rather than the wave table) may be used as the multiplier x input. This allows the amplitude of some complex signal (additive synthesis) to be controlled by a single ramp function (with the sacrifice of one oscillator). The multiplier y input may come from a register also. This allows one oscillator to amplitude modulate another oscillator. Finally the x and y inputs may both come from registers so that the outputs of two oscillators may be multiplied together. The multiplier options and the 15 general purpose registers provide a good deal of flexibility. For example, a second order filter section (two poles and two zeros) may be implemented using five oscillator sections.
The address, data in, and data out signals of the 15 registers are available to external devices for a .5 µsec period every 2 µsec. Data may be read from or written into any of these registers by an external device during this time. If no external address is supplied, the contents of the last register is put out during this time. In the simplest case, a signal from the synthesizer may clock the data to a D/A. However, more complex networks of these synthesizers and other units may be built by using some external circuitry for interconnection.
Control bits are provided so that the phase and ramp processes may be started and stopped synchronously. This allows the synthesizer to be used in a variety of non-real time application. For example, it could be used with a MUSIC V system as a peripheral processor where the synthesizer output data is read into the general purpose computer for further processing.
This versatile synthesizer provides on one compact card substantial real time capabilities. Combined with a floppy disc operating system for the LSI-11, a powerful synthesis system may be had for a relatively small price.
Pepino di Guigno
Server © IRCAM-CGP, 1996-2008 - file updated on .
Serveur © IRCAM-CGP, 1996-2008 - document mis à jour le .